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In the current situation, the reliability of a complex digital system is indigent owing to large amount of components, transistors, Integrated Circuits (ICs), etc. As a result the claim to design a good system with reliability is crucial. Such systems are frequently used in very critical applications such as bank transactions, defense communications, aerospace applications, etc. If these systems fail in the field, then the loss will be massive. The circuit designers carry on research to enhance the reliability of a system by adding redundancy like in hardware, software, information and time. The hardware redundancy is proposed to improve the reliability of the system. At present the Triple Modular Redundancy (TMR) is the most common technique used in the field of microelectronics to improve the reliability. This TMR system can tolerate one error for the correct output of the system. This paper primarily focuses on the 5MR scheme for the betterment of reliability which can tolerate two errors. The TMR in the 5MR system is implemented using FPGA Altera board with various voter circuits and ASIC implementation is carried out using ISCAS’85 and ISCAS’89 benchmark circuits. This paper analyze the 5MR system in detail using different majority computation circuits with TMR portion and convey the optimum circuit which will be suitable for low power, less area overhead and lesser delay.

Fault Tolerant Design using 5-Modular Redundancy Configuration with Different Voter Circuits