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High signal-to-noise ratio (SNR) image sensors are required in various areas; information equipment including smartphone, industrial measurement, medical, in-vehicle equipment, security, etc. To achieve a high SNR performance, some approaches, such as electron multiplication1)~3), using column amplifier4)5) or ADC6), and increasing conversion gain (CG) at floating diffusion (FD) 7)~9), have been reported. Recently, many researches aiming photon counting have been carried out actively8)~11). It is necessary to reduce the input referred noise to about 0.20e–rms for achieving the photon-countable sensitivity12)~16). Electron multiplying charge coupled device (EMCCD)2) and single photon avalanche diode (SPAD)3), which utilize electron multiplication effect, meet this performance and they are already used as single photon detectors. These photon counting imagers are available to distinguish whether or not one or more photons are incident at single exposure time, however, they cannot count the number of incident photons by one photon due to the following reasons; EMCCD uses electron multiplication effect, which is a stochastic event, with multiple stages, thus output signal distribution overlaps in-between different numbers of incident photons15)16). SPAD cannot distinguish one or more than one incident photons when more than one photons are incident during a single cycle of idle, build-up, quenching and recharge, thus it has a challenge in linearity11)15). Meanwhile, another approach to reduce the input referred noise is attempted; using 4transistor pixel CMOS image sensors. They have a good linearity and some of them achieved the noise level below 1.0e–rms5)17). Thus, it has a potential for photon counting. In the CMOS image sensor, increasing the gain at the input stage of the readout circuit is the most valid method to reduce the input referred noise. In that sense, increasing CG is the most effective way. Therefore, analysis and reduction of FD capacitance (CFD) components are extremely important. It should be noted that satisfying both high CG and high full well capacity (FWC) is also important. Though many analyses about parasitic capacitance of transistors have been reported in analog/digital fields18)~25), analysis of CFD in the CMOS image sensor based on the experiment has not been Abstract In this paper, we describe an analysis methodology of the components of floating diffusion (FD) capacitance (CFD) using the developed test element group (TEG) and propose a CFD reduction technology for photon-countable sensitivity. By analyzing the components of CFD, it was confirmed that the sum of them agreed well with CFD obtained by the photoelectric conversion characteristic in the image sensor and both the gate overlap capacitance and the p-n junction capacitance were large. The CFD reduction technology based on the result of analysis was applied to the FD and pixel source follower (SF). This technology is characterized by omitting lightly doped drain (LDD) implantation process, shallow and low concentration diffusion layer, and non-channel stop. Applying the reduction technology, we designed and fabricated a CMOS image sensor chip using 0.18μm 1-Poly-Si 5-Metal CMOS process technology with pinned photodiode (PD). It exhibited CFD of 0.66fF, conversion gain (CG) of 243μV/e– and input referred noise of 0.46e–rms.

[Paper] Analysis and Reduction Technologies of Floating Diffusion Capacitance in CMOS Image Sensor for Photon-Countable Sensitivity