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A heuristic algorithm for partitioning of VLSI circuits which attempts to minimize the number of branches cut between partitions is presented in this thesis. The algorithm uses a reduced connectivity matrix and the concept of cut index. The first phase of the algorithm, which is called the partitioning phase, finds the cut lines of the graph, and the second phase of the algorithm, which is called the optimization phase, optimize the branches cut by the partitions. The required computation time is shown to be bounded by O( n2 ), where n is the number of nodes in a graph. The proposed algorithm is currently implemented using X ·Window System. The program is called Reduced Connectivity Matrix Partitioning, abbreviated as rcmp. A universal netlist format used in the Tcmp allows it to interface to most existing VLSI CAD tools. Experimental results show that the proposed algorithm yields optimal solutions in most cases and near optimal solutions in some cases.

Partitionig of VLSI circuits using a reduced connectivity matrix