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Wireless communication and its applications have been growing rapidly in recent years. The driving force behind this development is the introduction of Digital Signal Processing (DSP) in the wireless communication world. While DSP functionality is highly integrated using Complementary Metal-Oxide-Semiconductor (CMOS) technology, current Front-End (FE) Integrated Circuits (ICs) depend on a mixture of semiconductor technologies, from GaAs to SiGe, making integration of the whole communication system on a single chip almost impossible. With the recent advance in CMOS technology, Radio Frequency (RF) CMOS IC design provides a potential solution for System-On-Chip (SOC). This dissertation explores the design of a fully integrated CMOS Low-Noise Amplifier (LNA) for an IEEE 802.11a wireless communication receiver. A new design methodology is presented for optimization of feedback to achieve simultaneous noise and gain match. Twoport noise theory is extended to multi-port noise analysis for a three-port-to-two-port noise transformation. This approach is applied in the design of a 5.3-GHz LNA in a CMOS 0.18um technology. The measurement gives averagely forward gain of 5.2 dB, input and output impedance matching of -9.3 dB and -8.9 dB respectively, isolation of -42.8 dB, estimated noise figure of 4.8 dB at frequency of 5.3-GHz with current consumption of 4.2-mA from a 1.5-V supply. A novel process-variation insensitive network is proposed to realize the onchip impedance matching that is immune to process variation. The proposed network utilizes precision matching capacitors to achieve a zero sensitivity to process variation. Its performance is demonstrated in Monte Carlo simulations.

Design of a low-noise amplifier for an IEEE802.11a wireless communication receiver