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A new algorithm for optimizing the thermal layout of basic VLSI elements, taking into account the features of the length of conductors and mutual thermal effects for 3D ICs, is described. It provides a differentiated temperature distribution in different layers of the chip. The algorithm includes parameters such as the length of the conductors, the interlayer transition holes, the power density and, consequently, the temperatures of the corresponding layers, and attempts to ensure a uniform temperature distribution in each layer of the chip. A fundamental difference from existing algorithms is the presence of two localization loops (inside the layer) and global (between layers), as well as using the metric for thermal homogeneity in topology. The novelty of the study lies in the parallel acquisition of a set of alternative solutions and the choice of a quasi-optic one from it. The principal difference lies in the work of the hybrid algorithm with the choice of volatile parameters. The experimental study was carried out for several randomly generated variants of the problem, and a number of well-known comparative tests of MCNC. Based on the results of the experiments, the algorithm showed an improvement in the value of the objective function by 5-10%. Keywords— thermal optimization, allocation algorithm, VLSI.

Algorithm of Thermal Optimization of Placement of Basic Elements of VLSI