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A 24 GHz programmable frequency divider in 65-nm CMOS process is presented in this paper. The divide ratio can be varied from 208 to 270 in a step size of 2.The divider consists of a divide-by-2, an 8/9 dual-modulus prescaler, a programmable pulse-swallow counter and a buffer. The post simulation results demonstrate that the divider can operate with the input frequency ranging from 16 GHz to 32 GHz while it draws 7.3 mA from a 1.2 V power supply.

Design of a 24 GHz Programmable Frequency Divider in 65-nm CMOS Process