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A novel Dual-Base Transistor (DUBAT) having a negative-resistance characteristic is presented. This device contains a lateral p-n-p Bipolar-Junction-Transistor (BJT) and a Hybrid-Mode Transistor, and is fabricated on silicon based 0.5μm CMOS process, compatible with the standard CMOS technology as distinct from the traditional DUBAT. The structure of BJT and the Hybrid-Mode Transistor is self-designed to have better current enhancement, didn’t use the standard component models provided by the process. The total size of the device is 20.55 μm×6.72 μm. The experimental results demonstrates that the average value of the negative resistance is about -1.04 kΩ, the DUBAT has a low valley current of 20.5970 μA, a high peak current of 1.2576 mA and a peak-to-valley current ratio of 61.06. The I-V characteristic of the device is also discussed in the paper. Introduction Negative resistance devices(NDR) are being increasingly used in integrated circuits. Such as oscillator circuits [1], digital logic gates [2] and memory circuits [3]. As a voltage-controlled differential negative resistance semiconductor device, the Dual-Base Transistor (DUBAT) has been researched since 1980 by Chung-Yu Wu and Ching-Yuan Wu [4]. Its theoretical model has been developed by Weilian Guo and Caihong Yu in 1994 [5]. A normal DUBAT is constructed by a p-n-p Bipolar Junction Transisitor (BJT) and a n-p-n BJT [4-6]. The BJTs could be lateral or vertical in substrate and the BUDATs were demonstrated in III-V compound semiconductor, SOI, Si/Ge or BiCMOS process but always can not be compatible with the mainstream CMOS technology[8,9]. As CMOS-compatible means wider application, less process difficulty, higher finished product rate and lower price, the research of CMOS-compatible Si-based NDR attracts more and more designers. In this paper, a novel DUBAT is designed and fabricated by using of the Si-based standard 0.5 μm CMOS process. In order to reduce the area occupation of the chip, the structure of the novel DUBAT is hand-engineered to be a there-terminals device instead of extracting device models from the standard library. This device contains a lateral p-n-p BJT and a Hybrid-Mode Transistor. A Hybrid-Mode Transistor is essentially a MOSFET whose source and drain diffusions serve as the emitter and the collector of BJT, the region between the source and drain serves as the base of the bipolar device. The gate is typically shorted to the emitter or collector[7]. The Hybrid-Mode Transistor can also be regarded as a BJT with an extra gate between the emitter and collector, and it works in a hybrid mode that involves both MOS and bipolar effects. The Device Structure A conventional DUBAT is constructed by a p-n-p BJT and a n-p-n BJT. The p-n-p BJT is worked as the feedback device and the n-p-n BJT is worked as the master device [4-6]. The electrical 4th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering (ICMMCCE 2015) © 2015. The authors Published by Atlantis Press 3013 equivalent circuit of the device is shown in Fig.1.(a) [5]. There are three terminals of DUBAT named as Base (B), Collector (C) and Emitter (E) marked respectively in Fig.1.(a). The collector and the base of n-p-n BJT are connected to the base and collector of the p-n-p BJT separately. The base-emitter voltage (VBE) of the DUBAT is fixed in a positive bias, the emitter is grounding, the collector-emitter voltage (VCE) is fixed in a changing positive bias. In this article, the n-p-n BJT is displaced by a n-channel depletion MOSFET which is working as a Hybrid-Mode Transisitor. (a) (b) Fig.1 (a) Electrical equivalent circuit of a conventional DUBAT. (b) The basic device structure of the novel DUBAT Fig.1.(b) shows the basic structure of the novel DUBAT. There are two N-wells in the P-substrate, and the transistors are grown upon them respectively. The left one is lateral p-n-p BJT and the right one is n-channel depletion MOSFET working as a Hybrid-Mode Transistor. Different from common component models of the standard CMOS process, this n-channel depletion MOSFET is fabricated into a P-base layer which is used as the base region of the transistor. ICE-VCE Characterizations The typical ICE-VCE characteristic of DUBAT is shown in Fig.2 [10]. There are five regions in the curve marked as OA, AB, BC, CD, respectively represent the Positive-Resistance Region, the Negative-Resistance Region, the Cut-Off Region and the Breakdown Region. The principle of the negative resistance phenomenon is analyzed as follows. Fig.2. Basic ICE-VCE characteristic of the DUBAT with a fixed negative base voltage drive VBE A. Positive-Resistance Region: OA When VBE is fixed in a positive bias, and there is a very small positive voltage on VCE, the gate-source voltage of the MOSFET is positive and is equal to (VBE-VCE). So the inversion channel of the MOSFET is deeper, the drain current of the MOSFET is large. In this case, the forward voltage drop of the emitter-base junction of the p-n-p BJT is equal or less than the drain voltage, so the p-n-p BJT is breakover and operate in saturation with a large base current which is equal to the drain current of the MOSFET. The MOSFET is in linear region. B. Negative-Resistance Region: AB As the value of VCE increasing, the gate-source voltage of the MOSFET(equals to VBE-VCE) is redusing,the inversion channel of the Hybrid-Mode Transistor become shallower, the drain current (ID) which equals to the BJT’s base current(IB1) will be reduced. In the end, the BJT operates in the active region. As was shown in Fig.2, ICE decreases when the VCE increases, which makes the ICE/VCE curve AB the first negative-resistance region. As the Hybrid-Mode Transistor is still in linear region, the collector current ICE could be written as:

Research on a novel Dual-Base Transistor (DUBAT) in 0.5 m Standard Si-base CMOS Process