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This paper presents the novel research on the low power and low voltage CMOS integrated circuit design patterns and general methodologies. With the integrated circuit technology to the rapid development of the deep sub-micron and nanometer order of magnitude, how to reduce the power consumption of the integrated circuit has become equally important problem with speed, area, power consumption constraints to further improve the performance of the chip, and increase the cost of the integrated circuit. A high level of integration and the application of high-speed device, especially in today's mobile devices and battery power equipment of the large-scale promotion, makes the power dissipation problem is becoming more and more prominent. Our research combines the literature list of reviews to propose the novel implementation paradigm for better performance. The reliability of semiconductor devices in a large part of the way that is depends on the reliability design of the product. In the process of general product development, must be reasonably by means of reliability technology and the engineering design method can effectively improve the reliability of the product, to ensure the reliability of the products. Only in device design reliability basis to achieve high reliability of products. CMOS integrated circuit development up to now, traditional two-dimensional planar integration process has reached its integration density limit, in order to increase performance chip integration more transistors, it is necessary to increase the chip size, and chip size increased with the extension of basic global interconnect distance, the more the grim problem of interconnection to overcome interconnect bandwidth limitations, we must change design method. The advantage of the polycrystalline silicon integrated circuit and the design difficulty can be listed as follows. • Due to the polycrystalline silicon is made up of different grain size and phase velocity of grain boundary structure characteristics, each of the thin film transistor threshold voltage that carrier mobility and series resistance, resulting in the output characteristics of polycrystalline

Research on the Low Power and Low Voltage CMOS Integrated Circuit Design Patterns and Methodologies