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with the advantages of high integration, high reliability, fast processing speed and online programming, the field-programmable gate array (FPGA) has become a hotspot of the studies on digital communication systems. In a suppressed carrier digital communication system, the quality of carrier extraction has a profound effect on demodulation performance. The traditional analog Costas loop performs poorly due to the imbalance between In-phase branch and Quadrature branch and the limit of analog circuit such as zero drift. Adopting digital circuit designed by FPGA can balance both In-phase and Quadrature branch, avoid these problems effectively. The realization of traditional Costas loop occupies large resources of FPGA. This paper improves the traditional structure of Costas loop according to the characteristics of FPGA devices, introduces an improved structure of the Costas loop which reduces the number of multipliers and adders and improves operation speed and reliability. Keywords—Improved structure of the Costas loop; FPGA;FIR filter; Multiplier

Design and Implementation of an Improved Costas Loop Circuits by Using FPGA