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Green design features with ultra-low power consumption and ultra-low voltage supply. Considering on about 26mV is the silicon power fed limit, below 100mV level, two accurate ultra-compact I-V models for SMIC 0.18μm process Nand PMOS transistors will be extracted with which CMOS NOT gate and its amplifier are analyzed by comparing exponential power law and SPICE running tool. The modeling methodology on new device or circuit starts with a candidate for one region of features in a basic construction formulae set selected by mechanism standards, then compare the two classes of data resulted from in right side the input-output characteristic and in left side the respondings of your first to/or No.n candidate, to minimize the errors between the classes, doing in above steps in cycle, at last you met an apt of novel model group in state-of-theart kept in your mind. In general, the ultra-low subthrethod (~25mV) MOSFETs are related to the input signals in parameters. From the single MOSFET to the two tubes we iterated from the simulation results to those models’ grinded fruits in our computers, and focused on scanning the width length ratio. Our time-variant models are in form of e exponential term for NMOSFET and plus quadratic term for PMOSFET. All in all the works built up novel milestones for first author proposed brain health microelectronics (BHM). Keywords-ultra-low voltage; compact MOSFET models; CMOS NOT-gate; CMOS NOT-based amplifier

At 100mV Power Supply Accurate Ultra-Compact I-V Models for SMIC 0.18 µm Process MOS Transistors with Analyses of CMOS NOT Gate and Its Amplifier