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The objective of this paper is to evaluate the delay impact of staggered metal filling on the standard cells and their associated local interconnect on several metal levels. A Design of Experiment (DOE) is used to define a large range of filling pattern shapes and positions. This set of filling patterns is then inserted in a Ring Oscillator (RO). From the filled RO simulations, the RO delay is expressed as a function of the filling pattern features. The maximal timing error between the model and the simulation is 1.3%, validating the model. The filling impact on RO delay magnifies the one introduced by the front-end process variations (PVT). Consequently, the filling influence is introduced for the minimal, typical and maximal corners, defined now with Process (P), Voltage (V), Temperature (T) and Filling density (F) characteristics.

jics. journal of integrated circuits and systems

Study of the Metal Filling Impact on Standard Cells and their Associated Interconnects Using Ring Oscillators: Definition of the Metal Fill Corner Concept