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This work describes the development of an amplifier frequency doubler chain (AFDC) operating at around 300 GHz based on SiGe BiCMOS technology. The driver amplifier is based on the differential cascode configuration, which employs coupled-line transformers for compact design. The frequency doubler is based on the class-B topology, which is known for exhibiting a large output power with low DC power consumption. The integrated AFDC, which consists of the frequency doubler and the preceding driver amplifier, exhibited a measured peak output power and DC-to-RF efficiency of -0.9 dBm and 0.97%, respectively, along with a conversion gain of -0.1 dB. It operates from 284 to 328 GHz with a 0-dBm input signal, consuming a total DC power of only 84 mW. The chip size is 720 × 310 μm2, excluding RF and DC pads.

A SiGe BiCMOS Amplifier-Frequency Doubler Chain Operating for 284–328 GHz