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A scalable and highly accurate RF symmetrical inductor model (with model error of less than 5%) has been developed from more than 100 test structures, enabling device performance versus layout size trade-ofis and optimization up to 10GHz. Large conductor width designs are found to yield good performance for inductors with small inductance values. However, as inductance or frequency increases, interactions between metallization resistive and substrate losses render the use of large widths unfavorable as they consume silicon area and degrade device performance. These flndings are particularly important when exploiting the cost-efiective silicon-based RF technologies for applications with operating frequencies greater than 2.5GHz.

MODELING AND LAYOUT OPTIMIZATION TECHNIQUES FOR SILICON-BASED SYMMETRICAL SPIRAL INDUCTORS