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A process of fabricating an SRAM cell, comprised with four NMOS devices, and two PMOS devices, featuring a dual gate polycide structure, traversing both NMOS and PMOS device regions, and featuring buried contact regions used for connection of specific NMOS drain regions, and used for connection of specific PMOS regions, has been developed. The process features the simultaneous fabrication of polysilicon gate structures, on an underlying gate insulator layer, and polysilicon buried contact structures, formed directly on the semiconductor substrate. The creation of heavily doped regions, in area between the polysilicon gate structures, and the polysilicon buried contact structures, also result in the doping of both structures. Subsequent anneal procedures result in the formation of a buried contact region, underlying the polysilicon buried contact structure. The contact between the buried contact regions, and the adjacent heavily doped source/drain regions, result in the desired connection of several device drain regions.

Rigorous Coupled Wave Analysis of Radially and Azimuthally-inhomogeneous, Elliptical, Cylindrical Systems