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Huffman coding is very important technique in information theory. Compression technique is the technology for reducing the amount of data used to denote any content without decreasing the quality. Furthermore, Clock gating is an effective method for decreasing power consumption in a sequence design. It saves more power by dividing the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. This paper aim to design Huffman coding and decoding process with proposing a novel method of clock gating to achieve low power consumption. Huffman design is executed by expending ASIC design procedures. With the purpose of executing the encoder and decoder structures, 130 nm typical cell technology libraries are utilized for ASIC implementation. The simulations are completed by utilizing Modelsim tool. The design of coding and decoding process has been made using Verilog HDL language. Moreover, it carried out using Quartus II 14.1 Web Edition (64-Bit).

Implementation of Clock Gating for Power Optimizing in Synchronous Design