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Optimizing the holding voltage of SCR to avoid the latch-up risk has been focused on by researchers recent years. A holding voltage adjustment technique of SCR is presented and discussed in this paper, with the devices implemented in a 0.6μm SOI process. Based on the holding voltage calculation, an external resistor is paralleled with the parasitic Ptub resistor to reduce the effective resistance to keep the holding state, leading to higher holding voltage. The proposed SCR (PSCR) is investigated with Transmission Line Pulse generator (TLP). The characterization results show that the holding voltage of the proposed structure can be elevated by the paralleled external resistor Re, and the lower resistance of Re, the higher holding voltage can be achieved. Meanwhile, the connection methods of Re are investigated with different emitter ratios of QNPN, indicating the trade-off between the holding voltage and failure current.

A Holding Voltage Adjustment Technique of SCR for ESD Protection