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A new bumping process on a Si die by electroplating without a photo-resist-mold (PRM) was assessed for the three dimensional (3D) stacking of Si dice. In this process, solder bumps were deposited selectively onto the surface of a Cu plugged-through silicon-via (TSV) in a Si die. Since lithography related processes to make a PRM for solder bumping were omitted, it can reduce the production time and cost for bumping. The substrate was a Si wafer, and TSVs were produced by deep-ion-reactive-etching (DRIE). As an insulation layer, SiO2 was formed by high-density-plasma-chemical-vapor-deposition (HDPCVD) or wet oxidation method. A Ti adhesion and an Au seed layers were deposited by sputtering. Cu was plugged into the vias by pulsed direct-current (DC) electroplating. The backside of the Si wafer was ground by chemicalmechanical-polishing (CMP). Sn bumps were electroplated on the Cu plugged vias by a current supplied through a Cu-overplated layer (COL) on the vias surface. As experimental results, wet oxidation provided a uniform SiO2 thickness through the via depth, whereas the SiO2 thickness by HDPCVD decreased with the via depth. The Ti and Au thicknesses also decreased along the via depth. In electroplating for Cu plugging,

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging