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The paper explores the analog analysis and higher order derivatives of drain current (ID) at gate source voltage (VGS), by introducing channel engineering technique of 3D conventional and Wavy Junctionless FinFETs (JLT) as silicon germanium  (Si1-0.25Ge0.25) device layer. In view of this, the performances are carried out for different gate length (LG) values (15-30 nm) and current characteristics determined by maintaining constant ON current (ION 10-5) (A/μm) for both devices. With respect to this, a comparison has been made between these MOS structures at molefraction x = 0.25 and it was found that the electric field is perpendicular to the current flow which induces volume inversion approach. Accordingly, for the simulation study better channel controllability over the gate is observed for Wavy structures and high ID induces as the LG scales down. With respect to this the constant ION determine ID, transconductance (gm), transconductance generation factor (TGF) and its higher order terms (g\m, and g\\m) of the devices are studied with relaxed SiGe approximation. The extensive simulation study on short channel (SC) parameters are also performed and it is observed that the Wavy JL FinFET shows less sensitivity towards short channel effects (SCEs) over conventional one, therefore the dependency of N-type doping concentration (ND = 1.7x1019 cm-3) and metal workfunction (ϕM = 4.6 eV) are responsible to achieving reduced SCEs.

facta universitatis. series electronics and energetics/facta universitatis. series: electronics and energetics

Impact of channel engineering (Si1-0.25Ge0.25) technique on GM(transconductance) and its higher order derivatives of 3D conventional and wavy Junctionless FinFETs (JLT)