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Architecture of binary to residue number system encoder based on the moduli set {2n − 1,2n,2n + 1} with embedded modulo 2n + 1 channel in the diminished-1 representation, which can be used instead of the standard modulo 2n+1 channel, is presented. We consider the binary numbers with dynamic range of proposed moduli set which is 23n−2n. Within this dynamic range, 3n-bit binary number is partitioned into three n-bit parts and converted to residue numbers. The proposed architecture based on moduli set {2n−1,2n ,2n+1} with embedded diminished-1 encoded channel have been mapped on Xilinx FPGA chip. The proposed architecture can be utilized in conjunction with any fast binary adder without requiring any extra hardware.

Binary to RNS encoder for the moduli set {2n-1, 2n, 2n+1} with embedded diminished-1 channel for DSP application