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A novel fully complementary and fully differential asynchronous CMOS comparator architecture, that consists of a two-stage preamplifier cas- caded with a latch, achieves a sub-100 ps propagation delay for a 50mVpp and higher input signal amplitudes under 1.1V supply and 2.1mWpower consumption. The proposed voltage comparator topology features two differential pairs of inputs (four in total) thus increasing signal-to-noise ratio (SNR) and noise immunity through rejection of the coupled noise components, reduced even-order harmonic distortion, and doubled output voltage swing. In addition to that, the comparator is truly self-biased via negative feedback loop thereby eliminating the need for a voltage reference and suppressing the influence of process, supply voltage and ambient temperature variations. The described analog comparator prototype occupies 0.001mm2 in a purely digital 40 nm LP (low-power) CMOS process technology. All the above mentioned merits make it highly attractive for use as a building block in implementation of the leading-edge system-on-chip (SoC) data transceivers and data converters.

A double-differential-input/differential-output fully complementary and self-biased asynchronous CMOS comparator