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The recent analog to digital converters, with the successive approximation (SAR ADC), are widely used for their high speed, low power operation and accuracy. SAR ADC demands precise internal digital to analog converter (DAC). To save power, the DAC is mainly implemented using capacitors (CDAC). Its precision depends mostly on layout implementation which must minimize the various parasitic effects. This paper presents two new layout design approaches of CDAC for SAR ADC used in a pixel detector implemented in 180 nm SOI technology. The various types, topology, size of the capacitors, power consumption, layout area, speed, and any nonlinearities are discussed. First is a new layout design of the 10-bit split capacitor DAC with Metal-Insulator-Metal capacitors, and, the second, is a 8-bit binary-weighted DAC with Metal-Oxide-Metal capacitors. The new layout of the metal-oxide-metal capacitor topology provides better accuracy of the DAC. The layout styles for each of CDAC, with low parasitic capacitances, are shown. The post layout simulations confirm that both capacitor arrays have an integral, differential nonlinearity, less than one least significant bit without a calibration scheme.

A Capacitor DAC for Charge Redistribution Analog to Digital Converter with Successive Approximation