English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

The instantaneous luminosity of the LHC will be increased by up to a factor of three with respect to the original design value at Run-3 (starting 2021). The ATLAS Level-1 end-cap muon trigger in LHC Run-3 will identify muons by combining data from the Thin-Gap Chamber detector (TGC) and the New Small Wheel (NSW), which is a new detector and will be able to operate in a high background hit rate at Run-3, to suppress the Level-1 trigger rate. In order to handle data from both TGC and NSW, a new trigger processor board has been developed. The board has a modern FPGA to make use of Multi-Gigabit transceiver technology. The readout system for trigger data has also been designed with TCP/IP instead of a dedicated ASIC. This letter presents the electronics and its firmware of the ATLAS Level-1 end-cap muon trigger processor board for LHC Run-3.

Development of the New Trigger Processor Board for the ATLAS Level-1 Endcap Muon Trigger for Run-3