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ALICE is preparing a major upgrade for 2021.  Subdetectors upgrading their counting room DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to ~7800 front end cards).  Requirements are strict: for the clock the allowed jitter is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is a must.  A novel approach to implement clock forwarding -- using only the internal PLLs of the CRU's onboard FPGA, without using an external jitter clener PLL -- is presented.

Clock and Trigger Distribution for ALICE Using the CRU FPGA Card