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We are developing the vertex detector with a fine pixel CCD (FPCCD) for the international linear collider (ILC), whose pixel size is 5 x 5 μm. ILC physics program impose several design requirements, as high granularity and low occupancy. FPCCD also impose several requirements in the readout ASIC, mainly, fast readout speed, low noise and low power consumption as well. We present the status of the R&D in order to achieve those design requirements.

Progress in the development of the vertex detector with fine pixel CCD at the ILC