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This paper presents a modified 2D Discrete Wavelet Transform (DWT) architecture with a proposed 16bit Radix8 Booth multiplier. Existing architecture makes use of Canonic Sign Digit (CSD) representation and when replaced the CSD multiplier with the proposed 16-bit Radix8 Booth multiplier it achieves better performance with small area and low power. In proposed Radix-8 Booth multiplier, the necessary product terms are generated and the remaining terms are truncated. In this method, the n order bit required by the specific coefficient is obtained and the remaining n bits are truncated so that 2n bit output truncated to n bit. The modified 2D DWT architecture is proposed to enhance that it occupies less number of clock cycles, so that it improves in the speed of operation By comparing synthesis results for existing CSD multiplier and the proposed Radix-8 Booth multiplier achieves an improvement of nearly 29.02% Area Delay Product (ADP) and 26.13% Power Delay Product (PDP).

Power and Area Efficient Radix-8 Booth Multiplier for 2-D DWT Architecture