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The De-blocking filter is used in H.264 video codec for improving the quality of video. The De-blocking filter helps in removing the artifacts which are generated due to block based transform. In this research work, the Modified Filter Order (MFO)-Carry Select Adder (CSLA) based De-Blocking Filter (DBF) is introduced to improve the video quality, which is named as MFO-CSLA-DBF architecture. Conventional H.264 standard DBF requires more area due to a separate storage block of the horizontal and vertical data. To solve this problem, this paper implemented modified filter order architecture to reduce the memory and area for storing filter block data. The complexity of the boundary block has reduced by minimizing the boundary strength values. Furthermore, the CSLA design used for the data merging process in the DBF architecture instead of normal adder designs that also occupies less area in the MFO. The MFO-CSLA-DBF architecture improved the quality of the video by increasing Peak-toNoise Ratio (PSNR), Structure similarity Index Matrix (SSIM) for different resolutions such as Quarter Common Intermediate Format (QCIF-176×144) and Common Intermediate Format (CIF-352×288). This MFO-CSLA-DBF architecture was implemented in the Xilinx tool by using the Verilog code for the Virtex-6 FPGA device. In this research work experimental results showed that MFO_CSLA_DBF architecture has reduced hardware utilization of FPGA for DBF from 2-3 % compared to the traditional DBF technique.

An Efficient VLSI Implementation of De-Blocking Filter with CSLA for H.264