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Integrated circuit design has been growing for years into what is now a multibillion dollar industry. Behind each fabricated circuit are hundreds of test circuits, and most importantly, simulations to prove product efficacy. The work presented in this thesis provides a straightforward method for simulating an All-Digital Phased Locked Loop. Previous research has been conducted using MATLAB's Simulink environment, however it is shown to be considerably slower than MATLAB's script environment. For this reason, an ADPLL MATLAB Model is presented and shown to provide comparable closed loop results with decreased simulation times. Crucial in initial circuit testing and debugging. Through TIE and modulation peak analysis it is shown that the ADPLL MATLAB model handles modulations of the reference, and presents a correct lowpass-filter behavior. On top, it can lock to all output frequencies allowed by the DCO with the exceptions incurred by the DCO decoder.

5.75-7.14 GHz All Digital Phase Locked Loop MATLAB model with Novel Filter-to-DCO Frequency Decoder.