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This paper presents Cut Resubstitution; a heuristic algorithm for post-processing of technology mapping for LUT-based FPGAs to minimize area under depth constraint. The concept of Cut Resubstitution is iterating local transformation of an LUT network with considering actual area reduction without using Boolean matching. Cut Resubstitution iterates the following process. At first, Cut Resubstitution substitutes several LUTs in current network in such a way that another LUT is to be redundant. Then Cut Resubstitution eliminates the redundant LUT from network. Experimental results show that a simple depth-minimum mapper followed by Cut Resubstitution generates network whose area is 7%, 7%, 10% smaller than that generated by DAOmap for maximum number of inputs of LUT 4, 5, 6 on average. Our method is similar or slightly faster than DAOmap.

Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs