English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image processing applications. AUs involve multifunctions and have multiplier as the critical element. In this paper, we present design and implementation of high speed and area efficient AU using Vedic algorithm. The work uses a simple “vertical and crosswise sutra” of Vedic mathematics to produce low complexity Partial Product (PP) generation unit in multiplier which reduces critical delay. Implementation results using TSMC 180 nm CMOS process with CADENCE Encounter Digital Implementation of the proposed AU revealed delay and Area-Delay Product (ADP) reductions of 13.7% and 19.2% respectively compared to prior recent approaches.

VLSI IMPLEMENTATION OF HIGH SPEED AREA EFFICIENT ARITHMETIC UNIT USING VEDIC MATHEMATICS