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An optimum design with silicon-on-insulator (SOI) device structure was proposed to eliminate back gate bias effect of the lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) and to improve breakdown voltage. The SOI structure was characterized by low doping buried layer (LDBL) inserted between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter to affect the strong inversion condition in the back MOS capacitor of the new SOI diode. The optimum design of LDBL thickness for the SOI diode was 2.65 μm. Fur- thermore, the breakdown capability has been improved 11%. However, no analysis of device physic has been so far given for the substrate bias effect on SOI device breakdown voltage. In this paper, the analysis of the substrate bias effect for the lateral and vertical surface potential and electric field distribution in the off-state is firstly proposed, and a novel SOI device structure with a low doping buried layer (LDBL) is employed to eliminate the substrate bias effect. The 2-D simulations for the substrate effect are performed using the tool ISE-TCAD (9). BACK GATE BIAS EFFECT IN THE SOI DEVICE

the open electrical and electronic engineering journal

Optimum Design for Eliminating Back Gate Bias Effect of Silicon-oninsulator Lateral Double Diffused Metal-oxide-semiconductor Field Effect Transistor with Low Doping Buried Layer