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In this work, a proposed pipeline implementation of Data Encryption Standard DES algorithm on field programmable gate arrays (FPGAs) is introduced with multiple design versions. All these versions are described in Electronic Code Book mode (ECB) using the hardware description language VHDL (Very high speed integrated circuit hardware description language). These versions have differences in the architecture and the techniques that substitution boxes (S_BOXes) can be implemented. All these design were implemented on devices from XILINX and we achieved speeds of up to 4.23 Gbits/s. Besides, a comparative study is conducted between the proposed designs for DES algorithm, another design for DES (Full Rolling) and the other previous implementations based on many aspects as architecture, cost and performance.

Efficient Uses of FPGAS for Hardware Implementation of Data Encryption Standard