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Traditional ASIC implementations have the well known draw-back of reduced flexibility compared to software implementations. Since modern security protocols are increasingly defined to be algorithm independent, a high degree of flexibility with respect to the cryptographic algorithms is desirable. A promising solution which combines high flexibility with the sp eed and p hysical security of traditional hardware is the implementation of cryptographic algorithms on reconfigurable devices such as FPGA. In this paper we compare - in terms of area and speed- FPGA implementation of radix-a scalable Montgomery modular multiplier using retiming technique with ASIC implementation for different word sizes of operands. The simulation data were generated using Mentor Graphics CAD tools.  |

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FPGA Versus ASIC Implementation of Radix-8 Scalable Montgomery Modular Multiplier.(Dept.E) FPGA Versus ASIC Implementation of Radix-8 Scalable Montgomery Modular Multiplier (Dept.E)