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In this paper design of low voltage low power A fully recycling folded cascode amplifier is designed mostly all trasistors are in subthreshold region which allowes low voltage with low power dissipatioon.The proposed amplifier designed using possitive feedback technique. The proposed amplifier gives good performance over that of the conventional folded cascode (FC) amplifier. This amplifier implemented in cadence virtuoso 180nm CMOS technology and operated with a 600mV supply voltage, 900fF capacitor load. The proposed FRFC amplifier achieves 73.5dB DC gain (73.5 dB versus 55 dB) and better phase margin as 56 degrees. The amplifier consumes 7μW which make it suitable for low power bio medical applications. KeywordsFRFC: Fully Recycling Folded Cascode, FC: Folded Cascode Design And Analysis Of Low Voltage, Low Power Fully Recycling Folded Cascode Amplifier 177 Fig 1: Folded cascode amplifier In the above schematic the transistors M1,M2 are differential input pair. Current source is connected at M01, M0 transistors. M4, M5, M6, M7 transistors act as current mirror. Two bias voltages is given to M5, M6 and M3, M4. Table 1: Input specifications Value Vdd 0.6v Vss -0.6v Unity gain frequency >3MHz Phase margin 55-60deg Power consumption <10μwatts Slewrate >2v/μs

DESIGN AND ANALYSIS OF LOW VOLTAGE, LOW POWER FULLY RECYCLING FOLDED CASCODE AMPLIFIER