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We are using term smart in two contexts, one context it is able to monitor Time to Live (TTL) with integration of digital clock in network and other context is energy efficiency that comes with design of energy efficient digital clock using HSTL IO standards available on Virtex-5 FPGA. Digital clock will trigger alarm when it current value reaches nearer to TTL and alarm will continue when it goes beyond TTL. This work also deals with a research gap that electronics designer never bother about selection of Input Output Standards. Current researcher focus only on efficient coding but never focus on selection of energy efficient IO standards. After testing and implementation phase of digital clock, we conclude that HSTL-II is the most efficient in term of energy efficiency and HSTL-III18 is the least efficient in term of energy efficiency.

Smart Communication Network design with application of Energy Efficient Digital Clock for Monitoring of Time -To-Live (TTL)