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The paper is about the designing of the low power energy proficient Vedic multiplier on 28nm field programmable gate array. Our motive here is to design a low power energy efficient design and for that reason, we are doing our study on different types of LVCMOS IO standards: LVCMOS_15, LVCMOS_18, LVCMOS_25, LVCMOS_33. To verify the thermal aware design we have taken 5 different temperatures from five different areas 10C, 25C, 40C, 55C, 70C. There is 3.73%, 3.21%, 3.005%, 3.002% reduction in leakage power, there is 0.544%,0.71%,3.63%,1.21% reduction in MAT and there is 73.74%,70.43%,52.00%,61.93% reduction in JT for LVCMOS_15, LVCMOS_18, LVCMOS_33, LVCMOS_25 correspondingly as we level down ambient temperature from 70 C to 10 C.

Energy Power Efficient Vedic Multiplier Design on 28nm FPGA Using Vedic Formula ANURPYENA