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Silicon (Si) wafers are the most commonly used substrates of semiconductor  devices. The device design rule is miniaturization, and the device chip size  is being increased to improve device integration, requiring that Si wafers  be manufactured with higher flatness and larger diameters. The polishing  used as a finishing process of Si wafers, however, has a serious problem; it  is very difficult to set the appropriate conditions for polishing the Si  wafer while wearing the polishing pad stably to high flatness. In our  previous work, a method of optimizing polishing conditions based on  kinematical analysis was proposed to achieve high flatness of the wafer and  pad. The method, however, did not consider the effect of the relative motion  direction between the wafer and the pads as an important factor in polishing  behaviors. Therefore, in this study, an optimization method considering the  relative motion direction is newly developed, and a series of double-sided  polishings of silicon wafers shows that the wafer flatness calculated by the  method corresponds well with that in the polishing experiments. Furthermore,  to make the distribution of pad wear more uniform, the optimization of  polishing conditions, including the wafer carrier specifications, is  conducted, and the feasibility is clarified.

Optimization of Double-Sided Polishing Conditions to Achieve High Flatness: Consideration of Relative Motion Direction