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This paper presents a first-order delta-sigma (ΔΣ) capacitance-to-digital converter (CDC) with low noise characteristics and a reconfigurable resolution of 12 to 16 bits. The proposed ΔΣ CDC is implemented as a first-order ΔΣ modulator with switched capacitor (SC) integrator and comparator. The resolution can be reconfigured by the accumulator using the reconfigurable 12to 16-bit up-counter. ΔΣ schemes are widely used for low-noise applications owing to the ability of the ΔΣ modulator to reduce in-band white noise through its inherent noise-shaping characteristic. Low-frequency colored noises such as flicker (1/f ) noises still remain. In order to reduce the low-frequency colored noise component, a chopper stabilization technique is exploited using the SC integrator of the ΔΣ CDC. The proposed ΔΣ CDC also controls the offset calibration capacitors that adjust the DC offset. This is caused by a capacitor mismatch owing to process variation and the parasitic capacitance of the input capacitive sensor. The ΔΣ CDC is fabricated by using the standard 0.18 μm 1P6M complementary metal-oxidesemiconductor (CMOS) process with an active area of 0.66 mm2. The total current consumption for the 16-bit ΔΣ CDC is 141 μA with a 1.8 V supply.

Low-noise Reconfigurable 12- to 16-bit Delta-Sigma Capacitance-to-digital Converter with Chopper Stabilization Technique