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Most of the commercial tools for digital synthesis are designed for Register-Transfer-Level (RTL) and logic synthesis. Numerous wonderful books and papers are available for understanding the syntax and semantics of the VHDL language. There are also many books and papers written for VHDL synthesis; these articles generally focus on the syntax for describing logic blocks such as combinational circuits, flip-flops, and simple finite state machines as well as how a synthesizer may infer logic from a VHDL description. Most students, even after they have learned the language features, still encounter tremendous difficulty when they begin to use the VHDL to describe a digital system for synthesis. In this paper, we describe the essence of modeling digital functions and present a powerful concept, called clocking schedule, for writing a VHDL program for RTL and logic synthesis. This technique facilitates seamless integration of all the modules in a digital design. A motion-guide project is used to demonstrate the applications and effectiveness of the technique to RTL and logic synthesis using the VHDL. Based on our experience from an “Advanced Digital Design” course, the methodology is very instructive. The students appreciated the power of digital synthesis with the VHDL in a very short period of time.

Clocking Schedule And Writing Vhdl Programs For Synthesis