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As mobile devices become heavily energy constrained, the need for low power, energy efficient circuits has emerged. The application space varies from ultra low power devices such as body sensor networks (BSNs), to higher performance applications such as smart phones, tablets, and all other devices constrained by battery life. In order to reduce energy consumption and increase energy efficiency, voltage supplies are scaled down to take advantage of quadratic active energy savings. Static random access memory (SRAM) is a critical component in modern system on chips (SoCs), consuming large amounts of area and often on the critical timing path. SRAM is the most commonly used in cache designs due to its high speed and high density. In the past, conventional SRAM designs were able to take advantage of Moore’s law by simply reducing devices sizes and scaling down VDD. This has become increasingly difficult as devices enter the nanoscale range due to increased device variability and leakage. SRAM devices are typically minimum sized, which further compounds this problem. The increase in both variation and leakage leads to reduced read and write margins, making it more difficult to design low power SRAMs that meet frequency and yield constraints. In addition, as the capacity of SRAM arrays continues to increase, the stability of the worst case bitcell degrades. Therefore it has become increasingly important to evaluate the effect of VDD reduction on SRAM yield and performance. The goal of this work is to push the memory design space beyond its conventional bounds. Typically the minimum supply voltage (VMIN) of SRAMs is higher than that of conventional CMOS logic due to a higher sensitivity to device variation. In order to push SRAM designs past this apparent brick wall, new knobs have been introduced such as alternative bitcells and read and write assist methods which improve the robustness of SRAMs in the presence of variability. These knobs introduce new tradeoffs between energy, speed, area and yield which are difficult to evaluate because they are dependent on many factors such as technology node, bitcell architecture, and design constraints. In this work, we first investigate the tradeoffs in designing a subthreshold SRAM embedded in an ultra low power body sensor network. The result of this work is one of the first embedded subthreshold memories, capable of operation down to 0.3 volts. Next, we present a method for fast, accurate estimation of SRAM dynamic write VMIN, which we will show provides a speedup of 112X over statistical blockade at a cost of only 3% average error. Furthermore, we will evaluate the combination of new bitcell circuit topologies and circuit assist methods at reducing SRAM read and write VMIN. Next, we extend the functionality of an existing tool used for rapid design space exploration and optimization of SRAMs. The proposed extensions include: evaluation of read and write assist methods, support of multi-bank design evaluation, circuit and architectural level co-optimization engine, and yield evaluation. Finally, we propose a method for tracking PVT variations during the write operation in order to regain energy lost through over-conservative guard-banding. The anticipated contribution of this research is a set of methods and tools for pushing SRAM designs to lower operating voltages, increasing yields, and evaluating design tradeoffs.

Circuit and CAD Techniques for Expanding the SRAM Design Space