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In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to and due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is (), which is confirmed to be a small-area implementation.

Deign of Small-Area Dual-Port eFuse OTP Memory IP for Power ICs