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Wireless application such as cell phone, two-way radios and wifi has exploited recent transceiver technology. Transceiver which consist of transmitter and receiver is a crucial unit in a wireless communication system to ensure accurate data transmission can be performed. This accuracy is controlled by a unit in the transceiver, namely Phase-Locked Loop (PLL). A low power transceiver is important to prolong the life of battery in wireless devices. Frequecy dividers in the PLL is one of the major contributors to power dissipation. Therefore, this project proposed a low power frequency divider for Phase-Locked Loop system, which is a commonly used frequency synthesizer in Radio Frequency (RF) transceivers. In order to achive the target, forward body bias technique (FBB) is employed. FBB reduces threshold voltage by applying positive voltage across the source to body junction. This technique enable circuit operates at low supply voltage, hence consumes low power. The circuit design in this work is implemented using Silterra 0.13 μm CMOS technology. For the frequency divider, True Single Phase-Clock (TSPC) topology is used due to its simple circuit and less cost in fabrication compared to other topologies. The simulation results show that CMOS-FBB frequency divider can operate up to 5.0 GHz from 0.8 V supply voltage and only consumes 34.55 nW power. Compared to frequency divider using conventional CMOS, the CMOS-FBB technique succeeded in lowering the dissipated power by 99.98 %.

Low Power Frequency Divider Using Forward Body Bias Technique