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With the development of three-dimensional (3D) integrated packaging [3, 5], Through Silicon Via (TSV) has become one of the most promising technologies in realizing 3D stacking package[1, 21]. Advanced TSV technology can realize 3D heterogeneous integration[28], high speed, wide band, small size and high performance through vias and micro-bumps. TSV is an important physical and electrical connection between chips [19], and the reliability of TSVs affects considerably on the reliability of 3D integrated devices [18]. However, TSV technology faces many difficulties and challenges in processing [12, 16]. Moreover, its reliability has not been fully understood [15]. Thus it is of paramount significance to investigate stress evolution mechanism and thermo-mechanical reliability of copper-filled TSV. The thermo mechanical reliability of the TSV structure is one of the most concerned research fields at present [30]. In the typical TSV manufacturing process, copper is often used as the conductive material to fill the TSVs [14]. The mismatch between copper and silicon’s thermal expansion cofficient (CTE) is significant [11]. To be specific, under the condition of rapid temperature change, the expansion rate Stress evolution mechanism and thermo-mechanical reliability analysis of copper-filled TSV interposer Yuan Chen a,b, Wei Su b, Hong-Zhong Huang a*, Ping Lai b, Xiao-ling Lin b, Si Chen b