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Low power VLSI is key technology area enabling battery powered applications. The research work given here presents clock gating scheme based on signal range comparison for low power VLSI. The work at first stage is applied to FIR architectures. Further in second stage to study the usability of the proposed technique both in ASIC and FPGA applications, circuit level simulation is also carried out. Low power validation of the proposed clock gating scheme at circuit level is simulated at 130 nm technology using SPICE tools. Analyses are carried out to study the effectiveness of the clock gating scheme with respect to the presence of information in given 2's complement signal. In final stage to demonstrate an application for the clock gating scheme, the FIR filter is extended towards realizing the real time signal correlator consisting a Finite State Machine (FSM). All the blocks of filters and correlator are simulated initially through Modelsim and results are verified. Xilinx ISE tools are used to verify the synthesis aspects. Power analysis is carried out using Xilinx X power tool. The transposed FIR is more suitable for VLSI implementation and demonstrates power saving of 47% when compared with non clock gating based scheme. In circuit simulation results tt is observed that 21% of power saving is possible a teach subword register stage with the proposed clock gating scheme under 50% of probability for NO-Information (NOI) input signal conditions. The subword clock gated correlator results show power saving of 34% under given signal conditions. The research demonstrates improved clock gating mechanism suitable for most of DSP applications. The proposed clock gating scheme can be more effective in the context when signal is with less amplitude or for narrow band signal applications. The work finds application is several future low power VLSI applications.

Low Power Clock Gating Method with Subword based Signal Range Matching Technique