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The effective bandwidth of the dynamic random-access memory (DRAM) for the alternate row-wise/column-wise matrix access (AR/CMA) mode, which is a basic characteristic in scientific and engineer-ing applications, is very low. Therefore, we propose the window memory layout scheme (WMLS), which is a matrix layout scheme that does not re-quire transposition, for AR/CMA applications. This scheme maps one row of a logical matrix into a rectangular memory window of the DRAM to balance the bandwidth of the row- and column-wise matrix access and to increase the DRAM 10 bandwidth. The optimal window configuration is theoretically analyzed to minimize the total number of no-data-visit oper-ations of the DRAM. Different WMLS implementationsare presented ac-cording to the memory structure of field-programmable gata array (FPGA), CPU, and GPU platforms. Experimental results show that the proposed WMLS can significantly improve DRAM bandwidth for AR/CMA appli-cations, achieved speedup factors of 1.6x and 2.0x are achieved for the general-purpose CPU and GPU platforms, respectively. For the FPGA plat-form, the WMLS DRAM controller is custom. The maximum bandwidth for the AR/CMA mode reaches 5.94 GB/s, which is a 73.6% improvement compared with that of the traditional row-wise access mode. Finally, we apply WMLS scheme for Chirp Scaling SAR application, comparing with the traditional access approach, the maximum speedup factors of 4.73X, 1.33X and 1.56X can be achieved for FPGA, CPU and GPU platform, re-spectively. © 2013 The Institute of Electronics, Information and Communication Engineers.

Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access