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In recent years, much research interest has developed in image enhancement and haze removal techniques. With increasing demand for real time enhancement and haze removal, the need for efficient architecture incorporating both haze removal and enhancement is necessary. In this paper, we propose an architecture supporting both real-time Retinex-based image enhancement and haze removal, using a single module. Efficiently leveraging the similarity between Retinex-based image enhancement and haze removal algorithms, we have successfully proposed an architecture supporting both using a single module. The implementation results reveal that just 1% logic circuits overhead is required to support Retinex-based image enhancement in single mode and haze removal based on Retinex model. This reduction in computation complexity by using a single module reduces the processing and memory implications especially in mobile consumer electronics, as opposed to implementing them individually using different modules. Furthermore, we utilize image enhancement for transmission map estimation instead of soft matting, thereby avoiding further computation complexity which would affect our goal of realizing high frame-rate real time processing. Our FPGA implementation, operating at an optimum frequency of 125MHz with 5.67M total block memory bit size, supports WUXGA (1,920×1,200) 60 fps as well as 1080p60 color input. Our proposed design is competitive with existing state-of-the-art designs. Our proposal is tailored to enhance consumer electronic such as on-board cameras, active surveillance intrusion detection systems, autonomous cars, mobile streaming systems and robotics with low processing and memory requirements. key words: real time processing, FPGA, Retinex-based image enhancement, haze removal

ieice transactions on fundamentals of electronics, communications and computer sciences/ieice transactions on fundamentals of electronics, communications and computer science

An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation