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Data rate requirements, from consumer application to automotive and aerospace grew rapidly in the last years. This led to the development of a series of communication protocols (i.e. Ethernet, PCI-Express, RapidIO and SpaceFibre), which use more than one communication lane, both to speed up data rate and to increase link reliability. Some of these protocols, such as SpaceFibre, are able to detect real-time changes in the number of active lanes and to adapt the data flow appropriately, providing a flexible solution, robust to lane failures. This results in a real time varying data path in the lower layers of the data handling system. The aim of this paper is to propose the architecture of a hardware block capable of reading a fixed number of words from a host FIFO and shaping them on a real time variable number of words equal to the number of active lanes. key words: VLSI, multi-lane, high-speed, word re-ordering, SpaceFibre

ieice transactions on fundamentals of electronics, communications and computer sciences/ieice transactions on fundamentals of electronics, communications and computer science

A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case