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This paper is about the implementation of a novel booth encoder-decoder in a 0.35 μm CMOS technology. By introducing a new truth table, the gate level delay from inputs to partial products is reduced to two XOR logic gates plus one transistor which is the main advantage of the proposed architecture. Also, the gate count is reduced which reduces the power dissipation. In addition, because of similar paths from inputs to outputs, the latency for all paths becomes equal. Therefore, the output waveforms will be free of glitch. Post layout simulations demonstrate that the delay of the whole system is 350 ps.

Low latency, glitch-free booth encoder-decoder for high speed multipliers