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In this express, we have proposed an improved architecture for designing efficient modulo (2n − 2p + 1) multipliers on the condition n ≥ 2p. The proposed modulo (2n − 2p + 1) multipliers can improve the current state of the art by 7.7–42.5% in terms of area and 13.1–44.2% in terms of performance delay on the average or by 60.5% in terms of area with the equivalent delay performance.

ieice electronics express

An improved architecture for designing modulo (2&lt;i&gt;&lt;sup&gt;n&lt;/sup&gt;&lt;/i&gt;-2&lt;i&gt;&lt;sup&gt;p&lt;/sup&gt;&lt;/i&gt;+1) multipliers