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This paper proposes a novel scan disabling-based BISTAided Scan Test (BAST) scheme to reduce test data volume and test power. In this scheme, a linear feedback shift register (LFSR) with an extra input generates test vector for each slice in multiple scan chains according to a deterministic test set with don’t-care bits. A hold logic, which is inserted between the LFSR and the scan chains, holds the outputs of the LFSR when the held vector is compatible with next slices. With the hold operation, the hold logic also can be used to select the best vector by the hold logic among the generated vectors. Using the scan disabling technique, the generated or held vector will not be shifted into the scan chains unless it is compatible with its corresponding slice. An automatic test equipment (ATE) only needs to store the control signals, not test vectors. The proposed scheme, based on the standard scan and using any test set with don’t-care bits, is widely applicable and easy to deploy. Experimental results show the proposed scheme achieves a higher compression gain and lower test power than previous lowcost schemes for cases where the number of specified bits in the test set is relatively few.

A scan disabling-based BAST scheme for test cost and test power reduction