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A high resolution highly linear low spur fractional time-to-digital converter (FTDC) for All Digital PLL (ADPLL) is presented. This FTDC employs a linear high gain time amplifier (TAMP) and a spur reduction digital filter to eliminate the spurs at the output. Unlike conventional TDCs, no delay line is utilized in the new FTDC, and hence no mismatch error cancelation technique is required. The FTDC structure is verified in theory and via simulation using an 180nm CMOS technology. The results illustrate a time resolution of 5psec, differential nonlinearity (DNL) free dynamic range of about 350psec, and the total power consumption, apart from the clock generator, of nearly 3mW.

A high resolution highly linear low spur fractional time-to-digital converter (FTDC) for ADPLL